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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
FEATURES
* Fully integrated PLL * Four differential 3.3V or 2.5V LVPECL outputs * Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK input * Output frequency range: 31.25MHz to 700MHz * VCO range: 250MHz to 700MHz * Supports Spread Spectrum Clocking (SSC) * Parallel interface for programming counter and output dividers during power-up * Serial 3 wire interface * Cycle-to-cycle jitter: 20ps (typical) * Output skew: TBD * Output duty cycle: TBD * Full 3.3V or mixed 3.3V core, 2.5V output operating supply * 0C to 85C ambient operating temperature * Available in both standard and lead-free RoHS-complaint packages
XTAL_OUT
GENERAL DESCRIPTION
The ICS84314-02 is a general purpose quad output frequency synthesizer and a member of HiPerClockSTM the HiPerClockSTM family of High Performance Clock Solutions from ICS. When the device uses parallel loading, the M bits are programmable and the output divider is hard-wired for divide by 2 thus providing a frequency range of 125MHz to 350MHz. In serial programming mode, the M bits are programmable and the output divider can be set for either divide by 1, 2, 4 or divide by 8, providing a frequency range of 31.25MHz to 700MHz. Additionally, the device supports spread spectrum clocking (SSC) for minimizing Electromagnetic Interference (EMI). The low cycle-cycle jitter and broad frequency range of the ICS84314-02 make it an ideal clock generator for a variety of demanding applications which require high performance.
IC S
BLOCK DIAGRAM
VCO_SEL
PIN ASSIGNMENT
M3 M2 M1 M0
32 31 30 29 28 27 26 25 M4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Q0 Q1 Q2 nQ0 nQ1 nQ2 Q3 nQ3
VCO_SEL
nP_LOAD
XTAL_IN
24 23
XTAL_SEL TEST_CLK XTAL_IN OSC XTAL_OUT / 16 1 0
TEST_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR VCCO
M5 M6 M7 M8 VEE VCC VCCO
ICS84314-02
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
22 21 20 19 18 17
PLL
PHASE DETECTOR MR VCO 0 1 /M /2
Output Divider N /1 Serial Mode /2 Parallel/Serial Mode (Power-up Default) /4 Serial Mode /8 Serial Mode
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3
S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8
CONFIGURATION INTERFACE LOGIC
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84314AY-02
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REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
nP_LOAD input is initially LOW. The data on inputs M0 through M8 is passed directly to the M divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M bits can be hardwired to set the M divider to a specific default state that will automatically occur during power-up. In parallel mode, the N output divider is set to 2. In serial mode, the N output divider can be set for either /1, /2, /4 or /8. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fxtal x 2M fVCO = 16 The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 16MHz reference are defined as 125 M 350. The frequency out is defined as follows: fout = fVCO x 1 = fxtal x 2M x 1 N 16 N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK.
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. The ICS84314-02 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A parallel-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a 16MHz crystal, this provides a 1MHz reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS84314-02 support two input modes to program the M divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the
S_CLOCK
SERIAL LOADING
S_DATA S_LOAD
*NULL *NULL SSC0 **N1
t
S
**N0 M8
M7
M6
M5
M4
M3
M2
M1
M0
t
H
nP_LOAD
t
S
PARALLEL LOADING
M0:M8
M, N
nP_LOAD
t
S
t
H
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS TABLE 1A. N OUTPUT DIVIDER FUNCTION TABLE (SERIAL LOAD) TABLE 1B. SSC FUNCTION TABLE
N1 Logic Value 0 0 1 1
84314AY-02
N0 Logic Value 0 1 0 1
N Output Divide /1 /2 (Power-up Default) /4 /8
SSC0 0 1
SSC State Off (Power-up Default) TBD
*NOTE: The NULL timing slot must be observed.
**NOTE: "N" can only be controlled through serial loading.
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
Type Input Input Power Power Power Output Output Output Output Description
TABLE 2. PIN DESCRIPTIONS
Number 1, 2, 5 29, 30, 31 3, 4, 32 6 7 8, 17 9, 10 11, 12 13, 14 15, 16 Name M4, M5, M8, M0, M1, M2 M6, M7, M3 VEE VCC VCCO Q0, nQ0 Q1, nQ1 Q2, nQ2 Q3, nQ3
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS / LVTTL interface levels. Pullup Negative supply pin. Core power supply pin.
Output supply pins. Differential output for the synthesizer. LVPECL interface levels. Differential output for the synthesizer. LVPECL interface levels. Differential output for the synthesizer. LVPECL interface levels. Differential output for the synthesizer. LVPECL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted 18 MR Input Pulldown outputs nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register 19 S_CLOCK Input Pulldown on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge 20 S_DATA Input Pulldown of S_CLOCK. LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the dividers. 21 S_LOAD Input Pulldown LVCMOS / LVTTL interface levels. Power Analog supply pin. 22 VCCA Selects between the crystal oscillator or test clock as the PLL reference source. Selects XTAL inputs when HIGH. Selects 23 XTAL_SEL Input Pullup TEST_CLK when LOW. LVCMOS / LVTTL interface levels. 24 TEST_CLK Input Pulldown Test clock input. LVCMOS / LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input. XTAL_IN, 25, 26 Input XTAL_OUT is the output. XTAL_OUT Parallel load input. Determines when data present at M8:M0 27 nP_LOAD Input Pulldown is loaded into the M divider. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. 28 VCO_SEL Input Pullup LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE 4A. PARALLEL
AND
SERIAL MODE FUNCTION TABLE
Inputs Conditions S_CLOCK X X X L L X S_DATA X X X Data Data Data X Data Reset. Forces outputs LOW. Data on M inputs passed directly to the M divider. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. M divider and N output divider values are latched. Parallel or serial input do not affect shift registers. S_DATA passed directly to M divider as it is clocked.
MR H L L L L L L
nP_LOAD X L H H H H
M X Data Data X X X X
S_LOAD X X L L L
L H X H NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition
TABLE 4B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
VCO Frequency (MHz) 250 252 254 256 M Divide 125 126 12 7 128 256 M8 0 0 0 0 12 8 M7 0 0 0 1 64 M6 1 1 1 0 32 M5 1 1 1 0 16 M4 1 1 1 0 8 M3 1 1 1 0 4 M2 1 1 1 0 2 M1 0 1 1 0 1 M0 1 0 1 0
* * * * 696 348 698 349 700 35 0 NOTE 1: These M divide values and frequency of 16MHz.
* * * * * * * * * * 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 the resulting frequencies correspond to
* * * * * * * * 1 1 0 0 1 1 0 1 1 1 1 0 cr ystal or TEST_CLK input
TABLE 4C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE (SERIAL PROGRAMMING MODE ONLY)
Input N1 Logic 0 0 1 1 N0 Logic 0 1 0 1 N Divide 1 2 4 8 Output Frequency (MHz) Q0:Q3, nQ0:nQ3 Minimum Maximum 250 700 12 5 62.5 31.25 35 0 175 87.5
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REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
4.6V -0.5V to VCC + 0.5 V 50mA 100mA 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 85C
Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 TBD TBD Maximum 3.465 3.465 3.465 Units V V V mA mA
TABLE 5B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 3.3V5% OR 2.5V5%, TA = 0C TO 85C
Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 2.375 Typical 3.3 3.3 2.5 TBD TBD Maximum 3.465 3.465 2.625 Units V V V mA mA
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REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
Test Conditions Minimum 2 -0.3 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 Typical Maximum VCC + 0.3 0.8 150 5 200 Units V V A A A A A
TABLE 5C. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 3.3V5% OR 2.5V5%, TA = 0C TO 85C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage M0:M2, M4, M5, M8, MR, nP_LOAD, S_CLOCK, S_DATA, S_LOAD Input M3, M6, M7, High Current XTAL_SEL, VCO_SEL TEST_CLK M0:M2, M4, M5, M8, MR, nP_LOAD, S_CLOCK, Input S_DATA, S_LOAD Low Current M3, M6, M7, XTAL_SEL, VCO_SEL
IIH
IIL
TABLE 5D. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 3.3V5% OR 2.5V5%, TA = 0C TO 85C
Symbol VOH VOL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V
VSWING Peak-to-Peak Output Voltage Swing 0. 6 NOTE 1: Outputs terminated with 50 to VCCO - 2V. See "Parameter Measurement Information" section, "Output Load Test Circuit" diagrams.
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 3.3V5% OR 2.5V5%, TA = 0C TO 85C
Symbol Parameter Test Conditions Minimum Typical Maximum Units TEST_CLK; NOTE 1 10 40 MHz XTAL_IN, XTAL_OUT; Input Frequency 12 40 MHz fIN NOTE 1 S_CLOCK 50 MH z NOTE 1: For the input crystal and reference frequency range, the M value must be set for the VCO to operate within the 250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 167 M 466. Using the maximum frequency of 40MHz, valid values of M are 50 M 140.
TABLE 7. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level 12 Test Conditions Minimum Typical Fundamental 40 50 7 1 MHz pF mW Maximum Units
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REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
Test Conditions Minimum 31.25 20 TBD TBD 20% to 80% 5 5 5 5 5 5 30 0.4 7 10 50 1 33.33 0.6 460 Typical Maximum 700 Units MHz ps ps ps ps ns ns ns ns ns ns kHz % dB % ms
TABLE 8A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 85C
Symbol FMAX t jit(cc) t jit(per) t sk(o) tR / tF tS Parameter Output Frequency Range Cycle-to-Cycle Jitter ; NOTE 1, 3 Period Jitter, RMS; NOTE 1 Output Skew; NOTE 2, 3 Output Rise/Fall Time M to nP_LOAD Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M to nP_LOAD tH FM FMF SSCred odc Hold Time S_DATA to S_CLOCK S_CLOCK to S_LOAD SSC Modulation Frequency; NOTE 4 SSC Modulation Factor ; NOTE 4 Spectral Reduction; NOTE 4 Output Duty Cycle
PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Jitter performance using cr ystal inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Spread Spectrum clocking enabled.
TABLE 8B. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 2.5V5%, TA = 0C TO 85C
Symbol FMAX t jit(cc) t jit(per) t sk(o) tR / tF tS Parameter Output Frequency Range Cycle-to-Cycle Jitter ; NOTE 1, 3 Period Jitter, RMS; NOTE 1 Output Skew; NOTE 2, 3 Output Rise/Fall Time M to nP_LOAD Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M to nP_LOAD tH FM FMF SSCred odc tLOCK
84314AY-02
Test Conditions
Minimum 31.25
Typical 20 TBD TBD
Maximum 700
Units MHz ps ps ps ps ns ns ns ns ns ns
20% to 80% 5 5 5 5 5 5 30
460
Hold Time
S_DATA to S_CLOCK S_CLOCK to S_LOAD
SSC Modulation Frequency; NOTE 4 SSC Modulation Factor ; NOTE 4 Spectral Reduction; NOTE 4 Output Duty Cycle PLL Lock Time
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33.33 0.4 0.6 10 50 1
kHz % dB % ms
7
See notes in Table 8A above.
REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V 2.8V0.04V 2V
Qx
V CC , VCCA, VCCO
Qx
SCOPE
VCC , VCCA V CCO
SCOPE
LVPECL
nQx
LVPECL
VEE
nQx
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx Qx nQy Qy
tsk(o)
nQx Qx tcycle n

VOH VREF VOL
tcycle n+1
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
80%
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
80% VSW I N G
Clock Outputs
Histogram
20% tR tF
20%
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
PERIOD JITTER
nQ0:nQ3 Q0:Q3
OUTPUT RISE/FALL TIME
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84314-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F VCCA .01F 10F 10
FIGURE 2. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. TEST_CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the TEST_CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
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REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
lel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
CRYSTAL INPUT INTERFACE
The ICS84314-02 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 3 below were determined using a 25MHz, 18pF paral-
XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332
Figure 3. CRYSTAL INPUt INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125 125
FOUT
FIN
Zo = 50 FOUT FIN
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
Zo = 50 84 84
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
84314AY-02
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REV. B NOVEMBER 17, 2005
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ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
close to ground level. The R3 in Figure 5A can be eliminated and the termination is shown in Figure 5C.
TERMINATION
FOR
2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
2.5V VCCO=2.5V Zo = 50 Ohm +
2.5V 2.5V VCCO=2.5V R1 250 Zo = 50 Ohm R3 250 +
Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
2,5V LVPECL Driv er R2 62.5 R4 62.5 Zo = 50 Ohm
-
R3 18
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. B NOVEMBER 17, 2005
PRELIMINARY
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ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board.
LAYOUT GUIDELINE
The schematic of the ICS84314-02 layout example used in this layout guideline is shown in Figure 6A. The ICS84314-02 recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general
Logic Input Pin Examples
C1 X1 C2 VCC
Set Logic Input to '1'
RU1 1K
VCC
Set Logic Input to '0'
RU2 Not Install
U1
32 31 30 29 28 27 26 25
ICS84314_02 VCC VCCO 24 23 22 21 20 19 18 17 C3 0.1u Zo = 50 Ohm R7 10 VCCA C11 0.01u C16 10u
M3 M2 M1 M0 VCO_SEL nP_LOAD X_OUT X_IN
VCCO VCC VCC
1 2 3 4 5 6 7 8
M4 M5 M6 M7 M8 VEE VCC VCCO
T_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR VCCO
To Logic Input pins
RD1 Not Install RD2 1K
To Logic Input pins
C4 0.1u
9 10 11 12 13 14 15 16
C5 0.1u
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3
+
Zo = 50 Ohm
-
VCC=3.3V VCCO=3.3V
C6 (Option) 0.1u
R2 50
R1 50
R3 50
Zo = 50 Ohm +
Zo = 50 Ohm
-
R5 50
R4 50
C7 (Option) 0.1u
R6 50
FIGURE 6A. SCHEMATIC OF 3.3V/3.3V RECOMMENDED LAYOUT
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The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
* The traces with 50 transmission lines TL1 and TL2 at FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock trace on the same layer. Whenever possible, avoid any vias on the clock traces. Any via on the trace can affect the trace characteristic impedance and hence degrade signal quality. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace. * Make sure no other signal trace is routed between the clock trace pair. The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination schemes can also be used but are not shown in this example.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15 as close as possible to the power pins. If space allows, placing the decoupling capacitor at the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. Maximize the pad size of the power (ground) at the decoupling capacitor. Maximize the number of vias between power (ground) and the pads. This can reduce the inductance between the power (ground) plane and the component power (ground) pins. If VCCA shares the same power supply with VCC, insert the RC filter R7, C11, and C16 in between. Place this RC filter as close to the VCCA as possible.
CLOCK TRACES AND TERMINATION
The component placements, locations and orientations should be arranged to achieve the best clock signal quality. Poor clock signal quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The trace shape and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins 25 (XTAL_IN) and 26 (XTAL_OUT). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces.
FIGURE 6B. PCB BOARD LAYOUT FOR ICS84314-02
84314AY-02
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REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
The ICS84314-02 triangle modulation frequency deviation will not exceed 0.6% down-spread from the nominal clock frequency (+0.0% / -0.5%). An example of the amount of down spread relative to the nominal clock frequency can be seen in the frequency domain, as shown in Figure 7B. The ratio of this width to the fundamental frequency is typically 0.4%, and will not exceed 0.6%. The resulting spectral reduction will be greater than 7dB, as shown in Figure 7B. It is important to note the ICS84314-02 7dB minimum spectral reduction is the component-specific EMI reduction, and will not necessarily be the same as the system EMI reduction.
SPREAD SPECTRUM
Spread-spectrum clocking is a frequency modulation technique for EMI reduction. When spread-spectrum is enabled, a 30kHz triangle waveform is used with 0.5% down-spread (+0.0% / -0.5%) from the nominal 200MHz clock frequency. An example of a triangle frequency modulation profile is shown in Figure 7A below. The ramp profile can be expressed as: * Fnom = Nominal Clock Frequency in Spread OFF mode (200MHz with 16MHz IN) * Fm = Nominal Modulation Frequency (30kHz) * = Modulation Factor (0.5% down spread) (1 - ) fnom + 2 fm x x fnom x t when 0 < t < 1 , 2 fm (1 - ) fnom - 2 fm x x fnom x t when 1 < t < 1 2 fm fm
Fnom
- 10 dBm
B
A
0.5/fm 1/fm
FIGURE 6A. TRIANGLE FREQUENCY MODULATION
FIGURE 6B. 200MHZ CLOCK OUTPUT
(A) SPREAD-SPECTRUM OFF (B) SPREAD-SPECTRUM ON
84314AY-02
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14
(1 - ) Fnom
= 0.4%
IN
FREQUENCY DOMAIN
REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER RELIABILITY INFORMATION
TABLE 9. JAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84314-02 is: 5051
84314AY-02
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15
REV. B NOVEMBER 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 10. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc
Reference Document: JEDEC Publication 95, MS-026
84314AY-02
MINIMUM
NOMINAL 32
MAXIMUM
1.60 0.05 1.35 0.30 0.09 9.00 BASIC 7.00 BASIC 5.60 9.00 BASIC 7.00 BASIC 5.60 0.80 BASIC 0.45 0 0.60 0.75 7 0.10
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REV. B NOVEMBER 17, 2005
0.15 1.40 0.37 1.45 0.45 0.20
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE 11. ORDERING INFORMATION
Part/Order Number Marking Package Shipping Packaging Temperature ICS84314AY-02 ICS84314AY02 32 Lead LQFP tray 0C to 85C ICS84314AY-02T ICS84314AY02 32 Lead LQFP 1000 tape & reel 0C to 85C ICS84314AY-02LF ICS84314A02L 32 Lead "Lead-Free" LQFP tray 0C to 85C ICS84314AY-02LFT ICS84314A02L 32 Lead "Lead-Free" LQFP 1000 tape & reel 0C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 84314AY-02
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REV. B NOVEMBER 17, 2005

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